| Device Utilization Summary (actual values) | [-] |
| Slice Logic Utilization | Used | Available | Utilization | Note(s) |
| Number of Slice Registers |
1,455 |
11,440 |
12% |
|
| Number used as Flip Flops |
1,451 |
|
|
|
| Number used as Latches |
0 |
|
|
|
| Number used as Latch-thrus |
0 |
|
|
|
| Number used as AND/OR logics |
4 |
|
|
|
| Number of Slice LUTs |
1,761 |
5,720 |
30% |
|
| Number used as logic |
1,598 |
5,720 |
27% |
|
| Number using O6 output only |
1,270 |
|
|
|
| Number using O5 output only |
48 |
|
|
|
| Number using O5 and O6 |
280 |
|
|
|
| Number used as ROM |
0 |
|
|
|
| Number used as Memory |
145 |
1,440 |
10% |
|
| Number used as Dual Port RAM |
64 |
|
|
|
| Number using O6 output only |
0 |
|
|
|
| Number using O5 output only |
0 |
|
|
|
| Number using O5 and O6 |
64 |
|
|
|
| Number used as Single Port RAM |
0 |
|
|
|
| Number used as Shift Register |
81 |
|
|
|
| Number using O6 output only |
24 |
|
|
|
| Number using O5 output only |
1 |
|
|
|
| Number using O5 and O6 |
56 |
|
|
|
| Number used exclusively as route-thrus |
18 |
|
|
|
| Number with same-slice register load |
14 |
|
|
|
| Number with same-slice carry load |
4 |
|
|
|
| Number with other load |
0 |
|
|
|
| Number of occupied Slices |
789 |
1,430 |
55% |
|
| Number of LUT Flip Flop pairs used |
2,204 |
|
|
|
| Number with an unused Flip Flop |
818 |
2,204 |
37% |
|
| Number with an unused LUT |
443 |
2,204 |
20% |
|
| Number of fully used LUT-FF pairs |
943 |
2,204 |
42% |
|
| Number of unique control sets |
109 |
|
|
|
Number of slice register sites lost
to control set restrictions |
420 |
11,440 |
3% |
|
| Number of bonded IOBs |
12 |
102 |
11% |
|
| Number of LOCed IOBs |
12 |
12 |
100% |
|
| IOB Flip Flops |
10 |
|
|
|
| Number of RAMB16BWERs |
4 |
32 |
12% |
|
| Number of RAMB8BWERs |
0 |
64 |
0% |
|
| Number of BUFIO2/BUFIO2_2CLKs |
1 |
32 |
3% |
|
| Number used as BUFIO2s |
1 |
|
|
|
| Number used as BUFIO2_2CLKs |
0 |
|
|
|
| Number of BUFIO2FB/BUFIO2FB_2CLKs |
0 |
32 |
0% |
|
| Number of BUFG/BUFGMUXs |
2 |
16 |
12% |
|
| Number used as BUFGs |
2 |
|
|
|
| Number used as BUFGMUX |
0 |
|
|
|
| Number of DCM/DCM_CLKGENs |
0 |
4 |
0% |
|
| Number of ILOGIC2/ISERDES2s |
1 |
200 |
1% |
|
| Number used as ILOGIC2s |
1 |
|
|
|
| Number used as ISERDES2s |
0 |
|
|
|
| Number of IODELAY2/IODRP2/IODRP2_MCBs |
0 |
200 |
0% |
|
| Number of OLOGIC2/OSERDES2s |
9 |
200 |
4% |
|
| Number used as OLOGIC2s |
9 |
|
|
|
| Number used as OSERDES2s |
0 |
|
|
|
| Number of BSCANs |
1 |
4 |
25% |
|
| Number of BUFHs |
0 |
128 |
0% |
|
| Number of BUFPLLs |
0 |
8 |
0% |
|
| Number of BUFPLL_MCBs |
0 |
4 |
0% |
|
| Number of DSP48A1s |
3 |
16 |
18% |
|
| Number of ICAPs |
0 |
1 |
0% |
|
| Number of MCBs |
0 |
2 |
0% |
|
| Number of PCILOGICSEs |
0 |
2 |
0% |
|
| Number of PLL_ADVs |
1 |
2 |
50% |
|
| Number of PMVs |
0 |
1 |
0% |
|
| Number of STARTUPs |
0 |
1 |
0% |
|
| Number of SUSPEND_SYNCs |
0 |
1 |
0% |
|
| Average Fanout of Non-Clock Nets |
3.87 |
|
|
|